description providing improved output current limiting, the udk, udn, and udq2559b, eb, and lb quad power drivers combine and logic gates and high-current bipolar outputs with complete output protection. each of the four outputs sink 700 ma in the on state. the outputs have a minimum breakdown voltage (load dump) of 60 v and a sustaining voltage of 40 v. the inputs are compatible with ttl and 5 v cmos logic systems. overcurrent protection for each channel has been designed into these devices and is activated at approximately 1 a. it protects each output from short circuits with supply voltages up to 25 v. when an output current trip point is reached, that output stage is driven linearly resulting in a reduced output current level. if an over-current or short-circuit condition continues, the thermal-limiting circuits will first sense the rise in junction temperature and then the rise in chip temperature, further decreasing the output current. under worst-case conditions, these devices will tolerate short circuits on all outputs, simultaneously. these devices can be used to drive various loads including incandescent lamps (without warming or limiting resistors) or inductive loads such as relays, solenoids, or dc stepping motors. the packages offer fused leads for enhanced thermal dissipation. package b is a 16-pin power dip with exposed tabs, eb is a 28-lead power plcc, and lb is a 16-lead power wide-body soic for surface-mount applications. the lead (pb) free versions have 100% matte tin leadframe plating. 29317.14g features and benefits ? 700 ma output current per channel ? independent overcurrent protection for each driver ? thermal protection for device and each driver ? low output-saturation voltage ? integral output flyback diodes ? ttl and 5 v cmos-compatible inputs protected quad power driver packages: functional block diagram (1 of 4 channels) not to scale 2559 16-pin dip with exposed thermal tabs (b package) 28-pin plcc (package eb) 16-pin soicw with internally fused pins (lb package)
protected quad power driver 2559 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number pb-free package packing ambient temperature (c) UDN2559B* ? 16-pin dip, exposed tabs 25 per tube ?20 to 85 UDN2559B-t yes 16-pin dip, exposed tabs 25 per tube udn2559eb* ? 28-lead plcc 38 per tube udn2559ebtr* ? 28-lead plcc 800 per reel udn2559eb-t yes 28-lead plcc 38 per tube udn2559lb* ? 16-lead soic 47 per tube udn2559lb-t yes 16-lead soic 47 per tube udq2559b* ? 16-pin dip, exposed tabs 25 per tube ?40 to 85 udq2559b-t yes 16-pin dip, exposed tabs 25 per tube udq2559lb* ? 16-lead soic 47 per tube udq2559lb-t yes 16-lead soic 47 per tube udk2559b ? 16-pin dip, exposed tabs 25 per tube ?40 to 125 udk2559b-t yes 16-pin dip, exposed tabs 25 per tube udk2559eb ? 28-lead plcc 38 per tube udk2559eb-t yes 28-lead plcc 38 per tube udk2559ebtr ? 28-lead plcc 800 per reel udk2559lb ? 16-lead soic 47 per tube udk2559lb-t yes 16-lead soic 47 per tube udk2559lbtr ? 16-lead soic 1000 per reel * certain variants cited in this footnote are in production but have been determined to be last time buy. this classification ind icates that the variant is obsolete and notice has been given. sale of the variant is currently restricted to existing customer application s. the variant should not be purchased for new design applications because of obsolescence in the near future. samples are no longer available . status date change october 29, 2007. deadline for receipt of last time buy orders is april 25, 2008. these variants include: UDN2559B, udn2559eb, udn2559ebtr, udn2559lb, udq2559b, and udq2559lb. absolute maximum ratings characteristic symbol notes rating units supply voltage v cc 7v input voltage range v in , v en 7v output voltage v out 60 v overcurrent-protected output voltage v out(p) 25 v output current i out outputs are peak current limited at approxi- mately 1.0 a per driver. see circuit description and application section for further information. 1.0 a operating ambient temperature t a range k ?40 to 125 oc range n ?20 to 85 oc range q ?40 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc
protected quad power driver 2559 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package eb 1 2 3 4 12 13 14 15 16 17 18 26 27 28 ground ground ground ground dwg. pp-019-1 k no connection enable supply nc nc cc v out 1 out 2 out 3 out 4 in 4 in 3 in 2 in 1 no connection k 19 20 21 22 23 24 25 5 6 7 8 9 10 11 package b 1 2 3 14 4 5 6 7 8 9 10 11 12 13 15 16 enable ground ground out 2 k ground ground out 3 out 4 k out 1 v cc in 1 dwg. pp-017-1 in 4 in 3 in 2 package lb 1 2 3 14 4 5 6 7 8 9 10 11 12 13 15 16 enable ground ground out 2 k ground ground out 3 out 4 k out 1 v cc in 1 dwg. pp-017-6 in 4 in 3 in 2 pin-out diagrams
protected quad power driver 2559 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com p d = (v out1 x i out1 x dc) + ? + (v outn x i outn x dc) + (v cc x i cc ) = (t j - t a )/r ja copyright ? 1995, 2002 allegro microsystems, inc. thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja package b, 2-layer pcb with 0.5 in. 2 exposed copper each side 43 oc/w package eb, 1-layer pcb with copper limited to solder pads 36 oc/w package lb, 1-layer pcb with copper limited to solder pads 90 oc/w *additional thermal information available on the allegro website
protected quad power driver 2559 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a = +25c (pre x ?udn?) or over operating temperature range (pre x ?udk? or ?udq?), v cc = 4.75 v to 5.25 v limits characteristic symbol test conditions min. typ. max. units output leakage current i cex v out = 50 v, v in = 0.8 v, v en = 2.0 v ? <1.0 100 a v out = 50 v, v in = 2.0 v, v en = 0.8 v ? <1.0 100 a output sustaining voltage v out(sus) i out = 100 ma, v in = v en = 0.8 v 40 ? ? v output saturation voltage v out(sat) all devices, i out = 100 ma ? ? 300 mv all devices, i out = 400 ma ? ? 500 mv b or eb package only, i out = 600 ma ? ? 700 mv over-current trip i trip ? 1.0 ? a input voltage logic 1 v in(1) or v en(1) 2.0 ? ? v logic 0 v in(0) or v en(0) ? ? 0.8 v input current logic 1 v in(1) or v en(1) = 2.0 v ? ? 40 a logic 0 v in(0) or v en(0) = 0.8 v ? ? -10 a total supply current* i cc all outputs on, v in = v en = 2.0 v ? ? 80 ma all outputs off ? ? 5.0 ma clamp diode forward voltage v f i f = 1.0 a ? ? 1.7 v i f = 1.5 a ? ? 2.1 v clamp diode leakage current i r v r = 50 v, d 1 + d 2 or d 3 + d 4 ? ? 50 a turn-on delay t phl i out = 500 ma ? ? 20 s t plh i out = 500 ma ? ? 20 s thermal limit t j ? 165 ? c typical data is for design information only. negative current is de ned as coming out of (sourcing) the speci ed terminal. as used here, -100 is de ned as greater than +10 (absolute magnitude convention) and the minimum is implicitly zero. * all inputs simultaneously, all other tests are performed with each input tested separately.
protected quad power driver 2559 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical output characteristic circuit description and application incandescent lamp driver high incandescent lamp turn-on/in-rush currents can contribute to poor lamp reliability and destroy semiconductor lamp drivers. warming or cur- rent-limiting resistors protect both driver and lamp but use signi cant power either when the lamp is off or when the lamp is on, respectively. lamps with steady-state current ratings up to 700 ma can be driven by these devices without the need for warming (parallel) or current-limiting (series) resistors. when an incandescent lamp is initially turned on, the cold lament is at minimum resistance and would normally allow a 10x to 12x in-rush cur- rent. with these drivers, during turn-on, the high in-rush current is sensed by the internal low-value sense resistor. drive current to the output stage is then diverted by the shunting transistor, and the load current is momentarily limited to approximately 1.0 a. during this short transition period, the output cur- rent is reduced to a value dependent on supply voltage and lament resistance. during lamp warmup, the lament resistance increases to its maximum value, the output stage goes into saturation and applies maximum rated voltage to the lamp. inductive load driver bi lar (unipolar) stepper motors, relays, or solenoids can be driven di- rectly. the internal yback diodes prevent damage to the output transistors by suppressing the high-voltage spikes that occur when turning off an inductive load. for rapid current decay (fast turn-off speeds), the use of zener diodes will raise the yback voltage and inprove performance. however, the peak voltage must not exceed the speci ed minimum sustaining voltage (v supply + v z + v f v out(sus) ). fault conditions in the event of a shorted load, the load current will attempt to increase. as described above, the drive current to the affected output stage is reduced, caus- ing the output stage to go linear, limiting the peak output current to approxi- mately 1 a. as the power dissipation of that output stage increases, a thermal gradient sensing circuit will become operational, further decreasing the drive current to the affected output stage and reducing the output current to a value dependent on supply voltage and load resistance. continuous or multiple overload conditions causing the chip temperature to reach approximately 165c will result in an additional reduction in output current to maintain a safe level. if the fault condition is corrected, the output stage will return to its normal saturated condition. typical output behavior
protected quad power driver 2559 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com eb package, 28-pin plcc with internally fused pins 5 through 11 and 19 through 25 2128 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area for reference only (reference jedec ms-018 ab) dimensions in millimeters 12.450.13 12.450.13 0.51 min c seating plane c 0.10 28x 11.510.08 5.210.36 5.210.36 0.740.08 5.210.36 0.430.10 5.210.36 11.510.08 0.51 1.27 4.37 +0.20 ?0.18 2 19.050.25 5.33 max 0.46 0.12 1.27 min 1 16 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area 6.35 +0.76 ?0.25 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 1.52 +0.25 ?0.38 0.38 +0.10 ?0.05 7.62 2.54 for reference only (reference jedec ms-001 bb) dimensions in inches, metric dimensions (mm) in brackets, for reference only b package, 16-pin dip with internally fused pins 4, 5, 12, and 13 and external thermal tabs
protected quad power driver 2559 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com lb package, 16-pin soicw with internally fused pins 4 and 5, and 12 and 13 9.50 0.65 2.25 1.27 c seating plane 1.27 0.25 0.20 0.10 0.41 0.10 2.65 max 10.300.33 7.500.10 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 10.300.20 c 0.10 16x 2 1 16 gauge plane seating plane for reference only pins 4 and 5, and 12 and 13 internally fused dimensions in millimeters (reference jedec ms-013 aa) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area a b reference pad layout (reference ipc soic127p1030x265-16m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b pcb layout reference view 2 1 16 copyright ?1995-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail speci cations as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cauti oned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon sibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com
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